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HV738DB1 HV738 65V 0.75A Ultrasound Pulser Demo Board
Introduction
The HV738 is a monolithic four channel, high speed, high voltage, ultrasound transmitter pulser. This integrated, high performance circuit is in a single 7x7mm, 48-lead QFN package. The HV738 can deliver up to 0.75A source and sink current to a capacitive transducer. It is designed for medical ultrasound imaging and ultrasound material NDT applications. It can also be used as a high voltage driver for other piezoelectric or capacitive MEMS transducers, or for ATE systems and pulse signal generators as a signal source. HV738's circuitry consists of controller logic circuits, level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of each channel are designed to provide peak output currents over 1.1A for pulsing, when MC0=1 and MC1=1, with up to 65V swings. When in mode 1, all the output stages drop the peak current to 140mA for low-voltage CW mode operation to save power. Two floating 8VDC power supplies, referenced to VPP and VNN, supply the P- and N-type power FET gate drivers. This pulser waveform's frequency upper limit is 20 MHz depending on the load capacitance. One HV738 can also be used as four damping circuits to generate fast return-to-zero waveforms by working with another HV738 as four pulsing circuits. It also has built-in under-voltage and over-temperature protection functions.
Designing a Pulser with HV738
This demo board data sheet describes how to use the HV738DB1 to generate the basic high voltage pulse waveform as an ultrasound transmitting pulser. The HV738 circuit uses the DC coupling method in all level translators. There are no external coupling capacitors needed. The VPP and VNN rail voltages can be changed rather quickly, compared to a high voltage capacitor gate coupled driving pulser. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. The input stage of the HV738 has high-speed level translators that are able to operate with logic signals of 1.2V to 5.0V and are optimized at 2.5V to 3.3V. In this demo board, the control logic signals are connected to a highspeed ribbon cable connector. The control signal logic-high voltage should be the same as the VCC voltage of the demo board, and the logic-low should be reference to GND. The HV738DB1 output waveforms can be displayed by using an oscilloscope probe directly connected to the test point TX1~4 and GND. The soldering jumper can select whether or not to connect the on-board equivalent-load, a 330pF, 200V capacitor, parallel with a 2.5k, 1W resistor. Also, a coaxial cable can be used to connect the user's transducer to easily drive and evaluate the HV738 transmitter pulser.
Application Circuit
+2.5V +8V +65V VPP-8V 0V to +65V
VCC OTP EN MC0 MC1 Logic Control PIN1 NIN1 GREF
VLL
VDD
VSUB
VPF
VPP
RGND Level Translator
P-Driver TXP1 HVOUT1
HV738
Level Translator TXN1 N-Driver GND 1 of 4 Channels Shown VSS GND VNF VNN RGND
VNN + 8V
0V to -65V
HV738DB1
The PCB Layout Techniques
The large thermal pad at the bottom of the HV738 package is connected to the VSUB pins to ensure that it always has the highest potential of the chip, in any condition. VSUB is the connection of the IC's substrate. PCB designers need to pay attention to the connecting traces as the output TXP1~4, TXN1~4 high-voltage and high-speed traces. In particular, low capacitance to the ground plane and more trace spacing need to be applied in this situation. High-speed PCB trace design practices that are compatible with about 50 to 100MHz operating speeds are used for the demo board PCB layout. The internal circuitry of the HV738 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors and the driver to the FET's gate-coupling capacitors should be as close to the pins as possible. The VSS pin pads should have low inductance feed-through connections that are connected directly to a solid ground plane. The VDD, VPP, VPF, VNF and VNN supplies can draw fast transient currents of up to 1.5A, so they should be provided with a low-impedance bypass capacitor at the chip's pins. A ceramic capacitor of up to 0.22 to 1.0F may be used. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise and using multiple HV738 ICs, insert another ferrite bead between VDD and decouple each chip supply separately. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of HV738's high voltage power stages are very low, in some cases it may be desirable to add a small value resistor in series with the output TXP1~4 and TXN1~4 to obtain better waveform integrity at the load terminals. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Be aware of the parasitic coupling from the outputs to the input signal terminals of HV738. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry.
Testing the Integrated Pulser
This HV738 pulser demo board should be powered up with multiple lab DC power supplies with current limiting functions. The following power supply voltages and current limits have been used in the testing: VPP=0 to +65V 5.0mA, VNN=0 to -65V 5.0mA, VDD=+8V 10mA, (VPP-VPF)=+8V 10mA, (VNF-VNN)=+8V 10mA. VCC=+2.5V 5.0mA for HV738 VLL does not include the user's logic circuits. The power-up or down sequences of the voltage supply ensure that the HV738 chip substrate VSUB is always at the highest potential of all the voltages supplied to the IC. The (VPP-VPF) and (VNF-VNN) are the two floating power supplies. They are only 8V, but floating with VPP and VNN. The floating voltages can be trimmed within the range of +7.5 to +10V to match the rising and falling time of the output pulses for the best HD2. Do not exceed the maximum voltage of +10V. The VPP and VNN are the positive and negative high voltages. They can be varied from 0 to +/-65V maximum. Note when the VPP=VNN=0, the VPF and VNF in respect to the ground voltage is -8V and +8V. The on-board dummy load 330pF//2.5k should be connected to the high voltage pulser output through the solder jumper when using an oscilloscope's high impedance probe to meet the typical loading conditions. To evaluate different loading conditions, one may change the values of RC within the current and power limit of the device. In order to drive piezo transducers with a cable, one should match the output load impendence properly to avoid cable and transducer reflections. A 70 to 75 coaxial cable is recommended. The coaxial cable end should be soldered to the TX1~4 and GND directly with very short leads. If a user's load is being used, the on board dummy load should be disconnected by cutting the small shorting copper trace in between the zero ohm resistors R7, R8, R9 or R10 pads. They are shorted by factory default. All the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may have limited input voltage. When using the probe on these high voltage test-points, make sure that VPP/VNN voltages do not exceed the probe limit. Using the high impendence oscilloscope probe for the on-board test points, it is important to have short ground leads to the circuit board ground plane. Precautions need to be applied to not overlap the logic-high time periods of the control signals. Otherwise, permanent damage to the device may occur when cross-conduction or shoot-through current exceed the device's maximum limits.
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HV738DB1
HV738DB1 Schematic
D1 BAV99 1 3 2 TX1 R7 0 C1 330p 250V TP1
VCC TP4
VDD
VSUB
VPF TP2 C8 1 100V
VPP
TP3
R1 2.55K 1W
TP25 TP5 C2 0.22 C3 0.22 C4 0.22 1 12 C5 1 100V 16 25 36 45 17 44
C7 0.22 C6 0.22
C9 1 100V 1
D2 BAV99 TP8 3 TX2 R8 0 C10 330p 250V R2 2.55K 1W
18 19 20 41 42 43
2
TP9 VCC 1 3 5 7 9 11 13 15 17 19 21 23 J1 TP6 2 4 6 8 10 12 14 16 18 20 22 24 EN NIN1 PIN1 NIN2 PIN2 NIN3 PIN3 NIN4 PIN4 OTP MC1 MC0 TP7 TP10
48 13 46 14 15
VS UB VS UB VS UB VS UB
R11 1K VLL OTP EN MC1 MC0
VDD VDD
VPP VPP VPP VPP VPP VPP
VPF VP F
TXP1 TXN1
34 33 TP14
TP15 TP11 TP12 TP13 TP17 TP18 TP19 3 4 5 6 7 8 9 10 PIN1 NIN1 PIN2 NIN2 PIN3 NIN3
TXP2
32 31 1 D3 BAV99 TP16 3 29 2 28 27 C11 330p 250V R3 2.55K 1W R9 0 TX3
U1 HV738K6
TXN2
TXP3 TXN3
30
TP20
TXP4 PIN4 NIN4 GREF VNN VNN VNN VNN VNN VNN VSS VSS VNF VNF TXN4 RGND RGND
HEADER 12X2
TP21
2 11
47
37 24
40 39 38 23 22 21
26 35
D4 BAV99 1 TP23 3 2 TX4 R10 0 C16 330p 250V
C13 C12 0.22 VNF 0.22 VNN C14 1 100V
TP22 C15 1 100V 0 R5
VCC VDD VCC VNF VPF VSUB 1 VSUB 1 VPP 1 VNN R12 1
VDD
VNN
VNF
VPF
VPP
VSUB
TP24
R6 2.55K 1W
6
3
6
BAT54DW-7
BAT54DW-7
4
D6A
D6B
D8A
D8B
D5 B1 10 0- 13
D7 B1 10 0- 13
D9 B1 10 0- 13
D10 B1 10 0- 13
R13 10
R14 10
R15 10
R16 10
R17 10
R4 10
VCC
VNN
VPP
VDD
VPP
J2 HEADER 8
+65V>VSUB>VPP VCC=+3.3V VDD=+8V (VPP-VPF)=+8V (VNF-VNN)=+8V VPP=0 to +65V VNN=0 to -65V
1
4
1
3
2
2
2
1
2
HV738DB1 PCB
1 2 3 4 5 6 7 8
3
HV738DB1
Board Voltage Supply Power-Up Sequence
1 2 3 4 5 6
VSUB VCC VDD VPF and VNF VPP / VNN
Logic Active
+65V>VSUB/VPP positive bias voltages +1.2 to 5.0V positive logic supply voltage +8V positive drive supply voltage Floating supply voltages, (VPP-VPF)=+8V and (VNF-VNN)=+8V 0 to +/-65V positive and negative high voltages Any logic control active high signals
Connector and Test Pin Description
Logic Control Signal Input Connector
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 VCC EN GND NIN1 GND PIN1 GND NIN2 GND PIN2 GND NIN3 GND PIN3 GND NIN4 GND PIN4 GND OTP GND MC1 GND MC0 VCC GND VDD VNN VNF VPF VPP VSUB Logic-high reference voltage input, VLL, +1.2 to 5.0V, normally from control circuit. Pulser output enable logic signal input, active high. Logic signal ground, 0V (2). Logic signal input for CH1 negative pulse output, active high. (1) Logic signal ground, 0V. Logic signal input for CH1 positive pulse output, active high. (1) Logic signal ground, 0V. Logic signal input for CH2 negative pulse output, active high. (1) Logic signal ground, 0V. Logic signal input for CH2 positive pulse output, active high. (1) Logic signal ground, 0V. Logic signal input for CH3 negative pulse output, active high. (1) Logic signal ground, 0V. Logic signal input for CH3 positive pulse output, active high. (1) Logic signal ground, 0V. Logic signal input for CH4 negative pulse output, active high. (1) Logic signal ground, 0V. Logic signal input for CH4 positive pulse output, active high. (1) Logic signal ground, 0V. Over temperature protection open drain output, active low, 1k pull up to VCC. Logic signal ground, 0V. Logic signal input of mode control MSB. Logic signal ground, 0V. Logic signal input of mode control LSB. Logic-high reference voltage supply, +1.2 to 5.0V current limit 5.0mA (if for VLL only). Low voltage power supply ground, 0V +8V positive driver voltage supply with current limit to 10mA. 0 to -65V Negative high voltage supply with current limit to 5.0mA Floating voltage supply (VNF-VNN)=+8V with current limit to 10mA. (3) Floating voltage supply (VPP-VPF)=+8V with current limit to 10mA. (3) 0 to +65V positive high voltage supply with current limit to 2.0mA Chip substrate bias voltage, must be (+65V>VSUB/VPP) with limit to 5.0mA
Power Supply Connector
Note: (1). Overlap control signals logic-high periods of PIN and NIN may cause the device permanent damage. (2). Due to the speed of logic control signal, every GND wire in the ribbon cable must connect to signal source ground. (3). (VPP-VPF) and (VNF-VNN) floating voltage can be trimmed from +7.5V to +10V for tr/tf time matching. Do not exceed the maximum +10V.
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HV738DB1
HV738DB1 Waveforms
Figure 1: Output waveform of 20MHz, VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-65V, MC0=MC1=1, HV738 TX4 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
Figure 2: Output waveform of 10MHz VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-65V, MC0=MC1=1, TX4 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
5
HV738DB1
Figure 3: Input to output propagation delay on rise is 17.6ns VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/65V, MC0=MC1=1, TX4 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
Figure 4: Input to output propagation delay on fall is 17.6ns. VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/65V, MC0=MC1=1, TX4 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
6
HV738DB1
Figure 5: Output rise and fall time is 31ns and 40ns. VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-65V, MC0=MC1=1, with load of 330pF//2.5k. TX1 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
Figure 6: Output waveform of 5MHz, VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-5.0V, MC0=MC1=1, with load of 330pF//2.5k. HV738 TX1 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
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HV738DB1
Figure 7: Output waveform of 5MHz, VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-5.0V, MC0=0, MC1=1, with load of 330pF//2.5k. TX1 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
Figure 8: Output waveform of 5MHz, VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-5.0V, MC0=1, MC1=0, with load of 330pF//2.5k. TX1 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
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HV738DB1
Figure 9: Output waveform of 5MHz, VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-5.0V, MC0=0, MC1=0, with load of 330pF//2.5k. TX1 via 200 and 20dB attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
Figure 10: Output waveform of 20MHz, VLL=2.5V, VDD=+8V, (VPP-VPF)=+8V, (VNF-VNN)=+8V, VPP/VNN=+/-5.0V, MC0=1, MC1=1, with load of 330pF//2.5k. TX1 via 200 and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50 oscilloscope input.
NR050107 9

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